1. Field of the Invention
The present disclosure relates to a memory transfer controller and method of transfer control for video line data and macroblock data. The memory transfer controller can be a bridge between a video system and a standard bus system for access to an external memory.
2. Description of the Related Art
The prior art has generally focused on the organization of data in memory and the use of controller circuits to facilitate the efficient transfer of video data between a video system and external memory.
U.S. Pat. No. 5,581,310 by Vinekar et al., entitled “Architecture for a High Definition Video Frame Memory and an Accompanying Data Organization for Use Therewith and Efficient Access Therefrom” describes an architecture for a memory with a wide word width particularly suited for use as a high definition video frame store memory and an accompanying organization for storing pixel data therein to facilitate efficient block and raster access therefrom. Specifically, the memory relies on storing n-byte words (n=m1×m2) across m2 independent memory segments with pre-defined positional offsets between m1-byte words stored in successive memory segments. All these segments are simultaneously accessed on a read or write basis. This structure of storage allows two widely differing forms of memory access, part of raster line or sub-block of macroblock, to be accessed easily using appropriate pipeline shuffling circuitry.
U.S. Pat. No. 5,892,522 by Moutin, entitled “Method and Apparatus for Addressing a Memory Area of MPEG Decoder”, describes a method and apparatus for addressing a memory area assigned to bi-directional images from a decoder according to an MPEG standard and organized in rows of macroblocks constituted by blocks containing data relative to a group of pixels of the image. The method, by dividing each data block into a half block of odd lines and a half block of even lines and then sequentially arranging all half-blocks of the same type in the same row of macroblocks, enables the reduction of memory area for storing bi-directional images.
U.S. Pat. No. 6,028,612 by Balakrishnan et al., “Picture Memory Mapping to Minimize Memory Bandwidth In Compression and De-compression of Data Sequences”, describes a method of partitioning the picture into 2 or more stripes, each having a pre-determined number of columns and sequentially mapping each row of the stripes to a subsequent word in memory that can reduce bandwidth when retrieving an array portion of the picture from memory. This was extended for the case of interlaced video sequences where a frame picture can be stored in a field organized memory with similar mapping schemes.
In a typical video encoding and decoding system, large amounts of video data are required to be transferred over a shared system bus, which may support other peripheral devices, especially for video encoding systems like MPEG-2, which eliminate temporal redundancy by motion estimation and inter-picture coding.
Optimal memory bandwidth usage is important for implementation. Some conventional methods that minimize bandwidth usage limit the data processing required to be performed, for example by implementing a smaller motion estimation search window or reducing or eliminating video pre- or post processing. Often, these methods achieve a lower bandwidth at the expense of encoded picture quality.
On the other hand, a faster and wider memory access can be developed to increase bandwidth to maintain picture quality. This can, however, increase power consumption and implementation complexity.
The problem of bandwidth usage can be described more specifically in relation to an MPEG compression system that consists of a video pre-processing sub-system that processes data at the video line rate and a video encoder sub-system that processes data at the macroblock rate. This represents two independent periodic data transfer events on the system bus.
The difference between video line data rate and macroblock data rate on the system bus gives rise to a situation, where both types of data transfers occur simultaneously, known as peak memory access bandwidth. This may cause unacceptable latency in data transfer which may crash the video pre-processor sub-system that is receiving digital data input in real time and may cripple the real time processing of the video encoder sub-system.
The worst case memory access bandwidth may be further aggravated where additional bus load is caused by other peripheral devices and or external memory access on the same system bus on top of the peak memory access bandwidth of the two sub-systems. This additional bus load may be unpredictable and difficult to control.
Solutions such as higher memory access and system bus throughput and/or using a larger memory buffer or usage of cache can improve efficiency but have the drawback of increasing implementation costs significantly.
During normal operation, the frequency of macroblock data transfer is higher than that of video line transfer. The video pre-processor sub-system requires video line data transfer at least every 64:s and 63.6:s for a PAL and NTSC system respectively. The video encoder sub-system requires macroblock data transfer at least every 24.7:s for a D1 picture.
On the other hand, the video line transfer has a larger amount of data transfer than the macroblock data transfer. For example, a luminance image video line transfer comprises of 720 bytes while the luminance image macroblock transfer comprises of 256 bytes.